Scientists at KAIST say they can now calculate how far transistors can shrink before quantum tunneling turns them into leaky little disasters. Their method does not promise smaller chips overnight, but it gives chip designers something they badly need: a way to estimate the lower limit of scaling before they spend years and money guessing.
The KAIST transistor shrinking limit arrives at a moment when the industry keeps talking up ”2-nm” manufacturing, even though the label no longer matches the physical dimensions in any simple way. As devices get smaller, the gap between marketing and physics gets wider, and quantum mechanics starts having the last laugh.
A density functional theory approach to transistor limits
The KAIST team built its method on density functional theory, a quantum physics tool already widely used to model electronic structures in molecules and materials. That matters because it lets researchers estimate, in advance and with useful accuracy, where a semiconductor structure stops behaving like an engineer’s tidy abstraction and starts behaving like a quantum object.
The core problem is tunneling: when transistors get too small, electrons can slip through barriers that should block them. In practice, that means more leakage current and less control over the current flowing between source and drain. Measuring that boundary directly is notoriously difficult, because the contact zone between a metal electrode and a semiconductor channel is tiny enough to make everyday lab precision look a bit optimistic.
MoS2 contacts gave the model its test case
To show the method works, the researchers used monolayer molybdenum disulfide, or MoS2, one of the better-known candidates for next-generation transistors. They modeled contacts with scandium, silver, gold, and palladium, and compared both top-contact and edge-contact layouts. That is a useful reminder that in nanoscale electronics, the interface often matters as much as the material itself.
- The tunneling limit is not fixed.
- It changes with the metal’s work function.
- It also depends on the contact geometry.
That flexibility is the real payoff. Instead of treating shrinkage as a blind race toward the smallest possible feature size, engineers can use the model to choose an electrode material and contact structure that push the limit farther down.
Less than 4 nm is still possible
According to KAIST’s calculations, the critical tunneling length can be reduced to less than 4 nm with the right combination of metal and contact design. For n-type devices, a top contact with a low-work-function metal looks strongest; for p-type devices, an edge contact with a high-work-function metal appears to be the better choice.
That does not mean mass production is about to follow. But it does give chipmakers a cleaner way to estimate contact resistance, leakage behavior, and the real scalability of 2D transistors before they commit to a fabrication run. Intel, TSMC, and Samsung have all spent years trying to tame this same scaling headache in different ways; the winner will be the company that can keep squeezing density without letting leakage eat the gains.
What chip designers will do with the result
The practical value here is not just in finding a number. It is in turning what used to be expensive trial and error into a more disciplined design process at the atomic level. If that holds up beyond the lab model, the next generation of transistor research may spend less time bumping into quantum limits and more time working around them.
The open question is whether this kind of modeling can keep pace with the industry’s appetite for ever-tighter nodes. Physics is still in charge, and it is not especially interested in roadmaps.