Intel slips $400M ASML High NA tool into laptop chips

High NA EUV shows up early on Intel 18A

High numerical aperture (High NA) extreme ultraviolet lithography was supposed to arrive at Intel’s 14A node toward the end of the decade. Instead, it has turned up early on Panther Lake, patterning layers that are also qualified to run on older EUV tools.

ASML said on Wednesday that Intel Foundry has entered high-volume manufacturing on a subset of its Core Ultra Series 3 chips, code-named Panther Lake, using High NA EUV. It is the first time any chipmaker has shipped a volume logic product patterned with the tool.

Panther Lake runs on Intel 18A, the node behind the chips that launched at CES in January and now ship in more than 200 laptop designs. For years, the plan was to hold High NA for 14A, the node after next; instead, it is now patterning what ASML calls “specific Intel 18A layers” at Hillsboro, Oregon.

What High NA actually buys

High NA is about resolution. Its optics gather light at a numerical aperture of 0.55, versus 0.33 for a standard EUV scanner, cutting the smallest printable feature from 13nm to 8nm in a single exposure.

Without that jump, chipmakers fall back to multiple patterning—exposing the same layer two or three times, with etch and deposition in between, to build a pattern the optics cannot resolve in one pass. Each extra exposure adds cost, stretches cycle time, and increases the chance that layers drift out of alignment.

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Single-exposure demonstrations at imec, on both logic and DRAM patterns, were early proof that one High NA pass could replace several standard EUV exposures.

The $400M tool and its limits

The hardware ramp has been fast. Intel and ASML integrated the industry’s first commercial High NA system at Hillsboro in 2024, and Intel passed acceptance testing on the second-generation TWINSCAN EXE:5200B in December, at 175 wafers an hour and 0.7nm overlay accuracy.

There is a catch, spelled out in ASML’s own release. The 18A layers in question are “dual-qualified”, certified to run on High NA and on older NXE EUV machines at matched yields. Panther Lake does not need High NA—Intel is using the scanner because it owns one, the wafers must come from somewhere, and every wafer through the machine generates data.

Naga Chandrasekaran, who runs Intel Foundry, framed it as capacity, not bragging rights. Qualifying the High NA option on select 18A layers means:

“our existing fleet of tools are providing customers with increased output, while we develop future options”

for later nodes.

Economics and TSMC’s hesitation

Cost is the core of the industry argument over when to switch to High NA. At roughly $400mn, a High NA scanner costs twice a standard EUV machine and images half the field, forcing a full-size pattern to be stitched from two exposures.

TSMC has been the conspicuous holdout. Chairman C.C. Wei told shareholders in June that the company owns High NA tools and is running research on them, and that cost is the only thing keeping them out of mass production. Its A13 and A12 nodes, both aimed at 2029, are not expected to require High NA.

That stance has only softened in tone since TSMC’s first public doubts in 2024.

Intel’s 14A and ASML’s upgraded outlook

For Intel, the real High NA node is still ahead. 14A is the next step, where High NA is designed in rather than bolted on. The node is on track for risk production in 2028, with the 0.9 process design kit due in October, the point at which prospective foundry customers commit to volumes.

The spending continues either way. Intel put €5bn into its Irish fab last week, one of the few EUV sites in Europe. Intel itself declined to comment on the Panther Lake / High NA announcement.

ASML, by contrast, had the better day. It raised 2026 revenue guidance to €43-45bn from €36-40bn on AI demand, and said it would expand both EUV and DUV capacity by 30% in each of the next two years.

Christophe Fouquet, ASML’s chief executive, told reporters in May that the first logic and memory products off High NA machines were months away. He was right, which is not the usual outcome for a lithography roadmap.