Why logic chips need a vertical route
The reason companies are piling transistors on top of each other is simple: planar scaling has become painfully expensive and physically awkward. More density still helps, especially for AI and high-performance computing, but the old trick of squeezing components closer together keeps running into leakage, heat, and isolation limits. Samsung’s vertical approach mirrors what NAND and HBM memory already did, only now the company is trying to drag logic into the same era.
Samsung says the new structure delivered good electrical behavior for both n-FET and p-FET devices, along with acceptable wafer-level uniformity. That is the sort of detail that separates a conference demo from a product roadmap, because chip makers can always show a neat diagram; making it repeatably manufacturable is where most bold claims go to die.
What Samsung says comes next
The company is treating this as the first brick, not the finished building. The next milestone is test circuitry such as SRAM blocks, which would help prove that full 3D logic can work beyond a lab sample. If Samsung gets that far, the payoff could be substantial: stacking transistors on the same footprint should improve energy efficiency and, in theory, performance, too.
For now, Samsung has stolen a lead in a field where rivals are also trying to break past flat-chip limits. The bigger question is whether this 42 nm demo becomes a manufacturing platform or just another impressive symposium slide. The industry has heard plenty of promises about the next transistor era; this one at least comes with a very small pitch.
Why logic chips need a vertical route
The reason companies are piling transistors on top of each other is simple: planar scaling has become painfully expensive and physically awkward. More density still helps, especially for AI and high-performance computing, but the old trick of squeezing components closer together keeps running into leakage, heat, and isolation limits. Samsung’s vertical approach mirrors what NAND and HBM memory already did, only now the company is trying to drag logic into the same era.
Samsung says the new structure delivered good electrical behavior for both n-FET and p-FET devices, along with acceptable wafer-level uniformity. That is the sort of detail that separates a conference demo from a product roadmap, because chip makers can always show a neat diagram; making it repeatably manufacturable is where most bold claims go to die.
What Samsung says comes next
The company is treating this as the first brick, not the finished building. The next milestone is test circuitry such as SRAM blocks, which would help prove that full 3D logic can work beyond a lab sample. If Samsung gets that far, the payoff could be substantial: stacking transistors on the same footprint should improve energy efficiency and, in theory, performance, too.
For now, Samsung has stolen a lead in a field where rivals are also trying to break past flat-chip limits. The bigger question is whether this 42 nm demo becomes a manufacturing platform or just another impressive symposium slide. The industry has heard plenty of promises about the next transistor era; this one at least comes with a very small pitch.
Why logic chips need a vertical route
The reason companies are piling transistors on top of each other is simple: planar scaling has become painfully expensive and physically awkward. More density still helps, especially for AI and high-performance computing, but the old trick of squeezing components closer together keeps running into leakage, heat, and isolation limits. Samsung’s vertical approach mirrors what NAND and HBM memory already did, only now the company is trying to drag logic into the same era.
Samsung says the new structure delivered good electrical behavior for both n-FET and p-FET devices, along with acceptable wafer-level uniformity. That is the sort of detail that separates a conference demo from a product roadmap, because chip makers can always show a neat diagram; making it repeatably manufacturable is where most bold claims go to die.
What Samsung says comes next
The company is treating this as the first brick, not the finished building. The next milestone is test circuitry such as SRAM blocks, which would help prove that full 3D logic can work beyond a lab sample. If Samsung gets that far, the payoff could be substantial: stacking transistors on the same footprint should improve energy efficiency and, in theory, performance, too.
For now, Samsung has stolen a lead in a field where rivals are also trying to break past flat-chip limits. The bigger question is whether this 42 nm demo becomes a manufacturing platform or just another impressive symposium slide. The industry has heard plenty of promises about the next transistor era; this one at least comes with a very small pitch.
Why logic chips need a vertical route
The reason companies are piling transistors on top of each other is simple: planar scaling has become painfully expensive and physically awkward. More density still helps, especially for AI and high-performance computing, but the old trick of squeezing components closer together keeps running into leakage, heat, and isolation limits. Samsung’s vertical approach mirrors what NAND and HBM memory already did, only now the company is trying to drag logic into the same era.
Samsung says the new structure delivered good electrical behavior for both n-FET and p-FET devices, along with acceptable wafer-level uniformity. That is the sort of detail that separates a conference demo from a product roadmap, because chip makers can always show a neat diagram; making it repeatably manufacturable is where most bold claims go to die.
What Samsung says comes next
The company is treating this as the first brick, not the finished building. The next milestone is test circuitry such as SRAM blocks, which would help prove that full 3D logic can work beyond a lab sample. If Samsung gets that far, the payoff could be substantial: stacking transistors on the same footprint should improve energy efficiency and, in theory, performance, too.
For now, Samsung has stolen a lead in a field where rivals are also trying to break past flat-chip limits. The bigger question is whether this 42 nm demo becomes a manufacturing platform or just another impressive symposium slide. The industry has heard plenty of promises about the next transistor era; this one at least comes with a very small pitch.
Why logic chips need a vertical route
The reason companies are piling transistors on top of each other is simple: planar scaling has become painfully expensive and physically awkward. More density still helps, especially for AI and high-performance computing, but the old trick of squeezing components closer together keeps running into leakage, heat, and isolation limits. Samsung’s vertical approach mirrors what NAND and HBM memory already did, only now the company is trying to drag logic into the same era.
Samsung says the new structure delivered good electrical behavior for both n-FET and p-FET devices, along with acceptable wafer-level uniformity. That is the sort of detail that separates a conference demo from a product roadmap, because chip makers can always show a neat diagram; making it repeatably manufacturable is where most bold claims go to die.
What Samsung says comes next
The company is treating this as the first brick, not the finished building. The next milestone is test circuitry such as SRAM blocks, which would help prove that full 3D logic can work beyond a lab sample. If Samsung gets that far, the payoff could be substantial: stacking transistors on the same footprint should improve energy efficiency and, in theory, performance, too.
For now, Samsung has stolen a lead in a field where rivals are also trying to break past flat-chip limits. The bigger question is whether this 42 nm demo becomes a manufacturing platform or just another impressive symposium slide. The industry has heard plenty of promises about the next transistor era; this one at least comes with a very small pitch.
Why logic chips need a vertical route
The reason companies are piling transistors on top of each other is simple: planar scaling has become painfully expensive and physically awkward. More density still helps, especially for AI and high-performance computing, but the old trick of squeezing components closer together keeps running into leakage, heat, and isolation limits. Samsung’s vertical approach mirrors what NAND and HBM memory already did, only now the company is trying to drag logic into the same era.
Samsung says the new structure delivered good electrical behavior for both n-FET and p-FET devices, along with acceptable wafer-level uniformity. That is the sort of detail that separates a conference demo from a product roadmap, because chip makers can always show a neat diagram; making it repeatably manufacturable is where most bold claims go to die.
What Samsung says comes next
The company is treating this as the first brick, not the finished building. The next milestone is test circuitry such as SRAM blocks, which would help prove that full 3D logic can work beyond a lab sample. If Samsung gets that far, the payoff could be substantial: stacking transistors on the same footprint should improve energy efficiency and, in theory, performance, too.
For now, Samsung has stolen a lead in a field where rivals are also trying to break past flat-chip limits. The bigger question is whether this 42 nm demo becomes a manufacturing platform or just another impressive symposium slide. The industry has heard plenty of promises about the next transistor era; this one at least comes with a very small pitch.
- Gate pitch: 42 nm
- Previous industry minimum: 48 nm
- Nanolists: three above and three below
- Vertical connection: RBC, or RX Bounded Contact
- Additional isolation: Middle Dielectric Isolation, or MDI
Why logic chips need a vertical route
The reason companies are piling transistors on top of each other is simple: planar scaling has become painfully expensive and physically awkward. More density still helps, especially for AI and high-performance computing, but the old trick of squeezing components closer together keeps running into leakage, heat, and isolation limits. Samsung’s vertical approach mirrors what NAND and HBM memory already did, only now the company is trying to drag logic into the same era.
Samsung says the new structure delivered good electrical behavior for both n-FET and p-FET devices, along with acceptable wafer-level uniformity. That is the sort of detail that separates a conference demo from a product roadmap, because chip makers can always show a neat diagram; making it repeatably manufacturable is where most bold claims go to die.
What Samsung says comes next
The company is treating this as the first brick, not the finished building. The next milestone is test circuitry such as SRAM blocks, which would help prove that full 3D logic can work beyond a lab sample. If Samsung gets that far, the payoff could be substantial: stacking transistors on the same footprint should improve energy efficiency and, in theory, performance, too.
For now, Samsung has stolen a lead in a field where rivals are also trying to break past flat-chip limits. The bigger question is whether this 42 nm demo becomes a manufacturing platform or just another impressive symposium slide. The industry has heard plenty of promises about the next transistor era; this one at least comes with a very small pitch.
Samsung says it has built the world’s smallest transistor designed for 3D chip stacking, a claim that points to where logic chips are heading now that brute-force shrinkage is running out of road. The company’s new 3D stacked FET uses a 42 nm gate pitch, beating the previous industry low of 48 nm and giving Samsung an early lead in the race to make vertical logic actually practical.
The work was shown at VLSI Symposium 2026 by engineers from Samsung Electronics’ Logic TD team. That matters because memory has been doing 3D for years, but logic has been the tougher beast: once spacing gets too tight, insulating layers start failing and the whole party ends in electrical crosstalk and yield problems. Vertical stacking sidesteps some of that pain by moving the separator between transistors out of the horizontal plane.
What Samsung changed in the 3D transistor design
Samsung’s demo pushed several pieces further at once. The channel uses six nanolists in total, with three placed above and three below, which the company says is the most used in a 3D-stacked transistor so far. Instead of the older C-shaped connection between upper and lower devices, Samsung switched to a direct vertical link using RBC, or RX Bounded Contact, which relies on narrow deep holes filled without voids.
- Gate pitch: 42 nm
- Previous industry minimum: 48 nm
- Nanolists: three above and three below
- Vertical connection: RBC, or RX Bounded Contact
- Additional isolation: Middle Dielectric Isolation, or MDI
Why logic chips need a vertical route
The reason companies are piling transistors on top of each other is simple: planar scaling has become painfully expensive and physically awkward. More density still helps, especially for AI and high-performance computing, but the old trick of squeezing components closer together keeps running into leakage, heat, and isolation limits. Samsung’s vertical approach mirrors what NAND and HBM memory already did, only now the company is trying to drag logic into the same era.
Samsung says the new structure delivered good electrical behavior for both n-FET and p-FET devices, along with acceptable wafer-level uniformity. That is the sort of detail that separates a conference demo from a product roadmap, because chip makers can always show a neat diagram; making it repeatably manufacturable is where most bold claims go to die.
What Samsung says comes next
The company is treating this as the first brick, not the finished building. The next milestone is test circuitry such as SRAM blocks, which would help prove that full 3D logic can work beyond a lab sample. If Samsung gets that far, the payoff could be substantial: stacking transistors on the same footprint should improve energy efficiency and, in theory, performance, too.
For now, Samsung has stolen a lead in a field where rivals are also trying to break past flat-chip limits. The bigger question is whether this 42 nm demo becomes a manufacturing platform or just another impressive symposium slide. The industry has heard plenty of promises about the next transistor era; this one at least comes with a very small pitch.