AMD and Intel have jointly defined a new set of AI-focused x86 instructions called ACE, a move that could eventually give their CPUs more efficient matrix math and inference support without forcing every workload through a discrete NPU or GPU. The catch: this is still a specification, not a shipped feature, and the first ACE-v1 processors are unlikely to reach the market before 2028.
The two rivals have been working together since the autumn of 2024 through the x86 Ecosystem Advisory Group, a rare case of cooperation in a business usually built on trench warfare. The point is obvious enough: Arm and RISC-V keep pushing harder into the same territory, and x86 vendors would rather standardize the AI plumbing than watch the market drift away one chip at a time.
What ACE is designed to do
ACE, short for AI Compute Extensions, is mainly about matrix multiplication using data formats suited to AI inference with quantized weights. The specification also defines a pile of format conversions, which matters because real-world AI code is rarely polite enough to stay in one neat numeric format.
Version 1.15 of the specification is available through the x86 Ecosystem Advisory Group, but it describes instructions only. Implementation details are still up to AMD, Intel, or anyone else who wants to build compatible hardware.
How ACE compares with Arm SME2
Arm has already locked in Scalable Matrix Extensions, or SME2, built on top of SVE2. Apple has used SME2 since the M4 generation, and Qualcomm has it in Snapdragon X2. That puts pressure on x86 to answer with something more than vague promises, especially as AI features become a standard sales pitch across laptops and desktops.
ACE will sit close to AVX and even share registers with it, while the spec also references AVX10 and Intel’s AMX. That is a fairly practical choice: x86 vendors are trying to extend existing vector machinery rather than bolt on yet another isolated island of silicon.
- ACE-v1 processors must support a defined subset of AVX10.2.
- ACE v1 introduces 11 data formats, some with multiple representations.
- The spec covers both computation and data-format conversion.
Why x86 still leans on NPUs
For now, x86 laptops and PCs already rely on NPUs for AI acceleration, but those blocks are narrowly optimized and take up a lot of die area. Microsoft made 40 TOPS INT8 NPU performance mandatory for Copilot+ branding in 2024, then loosened the rules and allowed GPUs too. If ACE lands as a flexible alternative, that policy could be rewritten again.
Still, don’t expect retail hardware tomorrow. AMD has not tied Zen 6 to ACE, Intel has not tied Nova Lake to ACE, and the most concrete hint so far is AMD’s mention of a Matrix Engine for Zen 7. That may end up being ACE by another name, or it may simply be the usual pre-launch tease with better branding.
The smarter bet is that ACE becomes the x86 industry’s answer to Arm’s matrix push only after a longer transition period, with early support showing up first in silicon roadmaps and software tooling. By then, the real competition may not be between CPU instruction sets alone, but between whichever platform can make AI acceleration feel standard instead of special.