The next fight in chipmaking is not about making transistors smaller for bragging rights. It is about finding out how far physics still allows them to shrink before electrons start leaking through the walls. Researchers at KAIST say they have built a quantum-mechanical way to estimate that limit, and in some transistor designs it drops below 4 nanometers.
That matters because the industry keeps talking up 2-nanometer-class manufacturing while the active parts of many transistors are still physically larger than 10 nanometers. The gap between marketing-friendly node names and the messy reality of device physics has never been especially elegant, and this is exactly where classical models stop being very helpful.
Quantum tunneling sets the real ceiling
The problem is quantum tunneling: electrons begin slipping through barriers that should, on paper, block them. Once that happens, current leaks where it should not, switching gets sloppy, and the transistor stops behaving like a tidy on-off gate. At atomic scales, even the contact between the metal electrodes and the semiconductor channel becomes hard to control with enough precision for clean experiments.
So the KAIST team used first-principles calculations, which means they modeled the materials directly from quantum mechanics rather than fitting the math to lab data. Their tool of choice was MS-DFT, a density-functional approach extended to simulate full devices and tricky metal-semiconductor interfaces, then paired with transfer length method calculations to study contact resistance in a digital setup.
MoS2, metal choice, and contact geometry
For the test case, the researchers used a monolayer of molybdenum disulfide, or MoS2, a one-atom-thick semiconductor that has become a favorite candidate for next-generation transistors. The model showed that electron penetration and leakage are shaped not just by the channel material, but by the metal’s work function and the geometry of the contact. In other words, the interface is not a footnote; it is the whole game.
- Measured in the model: tunneling depth and leakage current
- Variables that change the limit: metal work function and contact structure
- Test material: monolayer MoS2
The most useful finding is also the least glamorous: the minimum usable length is not a fixed number carved into silicon’s fate. It shifts with engineering choices, which means device makers can still move the goalposts by changing contacts and materials rather than waiting for physics to politely step aside. In some configurations, the team says the critical tunneling length can be pushed below 4 nanometers.
What chip designers can do with the result
That gives chip designers a more practical route than the usual race toward smaller nodes: simulate the device before building it, then mix different two-dimensional materials to cut power use and improve efficiency. It also reflects where the semiconductor industry is heading more broadly, as companies from Intel to TSMC keep leaning harder on new materials, advanced packaging, and interface engineering to extend scaling when plain old shrinking gets expensive.
The bigger shift is philosophical. Instead of treating transistor miniaturization as a guessing game capped by trial and error, this kind of modeling turns it into a design problem with measurable boundaries. The next question is whether the industry can translate that theoretical freedom into manufacturing that actually behaves at scale, because quantum mechanics is precise and fabs are famously less charming.