Huawei wants the chip industry to stop obsessing over how tiny transistors can get and start paying more attention to how fast signals move. At the International Circuit Systems Symposium hosted by the IEEE, the company introduced what it calls the ”Tao (τ) Law,” a proposal built around ”time shrinkage” rather than the familiar race for geometric shrinkage. The pitch is simple: if shrinking chips is getting harder, make them behave smarter instead.
That is a neat idea, and also a very convenient one for an industry running into physics, cost, and yield headaches all at once. The broader semiconductor world has been hunting for alternatives for years, from advanced packaging to chiplets, because brute-force miniaturization is no longer delivering the easy wins it once did.
What Huawei says Tao Law changes
Huawei’s argument is that performance should not depend only on making transistors smaller. Instead, the company wants to shorten the time it takes for signals to travel inside a chip, which could improve speed and efficiency even without a dramatic node shrink.
The centerpiece of that plan is ”logic folding.” Think of it as reorganizing chip logic into tighter layers so data has less distance to travel, while density rises at the same time. Huawei says the idea spans devices, circuits, chips, and full computing systems, which is a broad claim with just enough ambition to keep engineers and marketing teams equally busy.
- Focus: reducing signal delay instead of only shrinking transistors
- Main technique: logic folding
- Claimed scope: devices, circuits, chips, and computing systems
Kirin 2026 is the first commercial test
The first major product tied to this approach is expected to be Huawei’s next Kirin 2026 mobile chip, due later this autumn. Huawei says it has already designed and mass-produced 381 chips over the past six years using ideas linked to the new method, which suggests this is not just a slide-deck exercise.
If the company’s claims hold up, the payoff would be better performance and energy efficiency without waiting for traditional process shrinks to save the day. That is a timely message, because the rest of the industry has been leaning harder on architectural tricks, packaging, and software optimization as the old transistor playbook gets more expensive.
Huawei’s 1.4nm-style target by 2031
Huawei says chips built under Tao Law could eventually reach a transistor density comparable to advanced 1.4nm process technology within five years, with performance levels similar to future 1.4nm processors by 2031. The company is careful not to say it will literally manufacture a traditional 1.4nm chip, and that distinction matters. This is really an argument that smarter architecture can mimic the gains of a smaller node, at least on paper.
He Tingbo, president of Huawei Semiconductor Business, also used the event to stress cooperation, saying no single company can solve the industry’s scaling problem alone. That is probably true, although it is also the sort of line executives tend to love right after unveiling a bold new doctrine.
The real question now is whether Tao Law becomes a genuine engineering framework or just a more poetic way of describing the semiconductor industry’s pivot from size to efficiency. The upcoming Kirin 2026 chip should provide the first clue.